There is a tendency for modern memory chips to be manufactured in increasingly larger sizes. For example, in first-generation 256M DRAMs, the reported size of the memory chip is 14×25 mm. This means that the speed at which memory capacity increases is greater than the speed at which the resolution line width and cell size of the exposure apparatus is reduced.
Generally, in the case of a memory chip size of 256M and beyond, only one chip can be exposed per exposure in an exposure area having a diameter of 31 mm in a demagnifying projection exposure apparatus (stepper) used as an exposure apparatus for the critical layer. In order to raise throughput, therefore, an exposure apparatus having a larger exposure area is required.
A semiconductor-element exposure apparatus for the rough layer and a reflecting projection exposure apparatus for large screen liquid crystal displays such as monitors, which require a high throughput, are used widely as an exposure apparatus for exposing a large exposure area. These apparatuses are of the slit-scan exposure type, which rely upon so-called mask-wafer relative scanning, for linearly scanning a mask with illuminating light in the shape of an arcuate slit and exposing a wafer to the mask in one batch using a concentric reflecting-mirror optical system.
With exposure apparatuses of this type, measurement of height of the wafer and drive for correcting automatic focusing and an automatic leveling mechanism are carried out continuously during scanning exposure. This is to gradually match the exposure surface of a photosensitive substrate (a wafer or glass plate coated with a photoresist, or the like) with the optimum image-forming plane of the projection optical system.
In the height and surface position detection mechanism of these exposure apparatuses, a method employed is to sense reflected light from the photosensitive substrate as a positional deviation on a CCD or PSD sensor using a so-called oblique-incidence optical system in which light is made to impinge upon a wafer surface from above at an angle. With a method of this kind, height is measured at a plurality of measurement positions during scanning, and the amount of drive correcting the height and inclination of the wafer surface at such a time that the measurement position passes the exposure slit area is calculated and corrected based upon a plurality of measured values of height of the wafer surface.
In a case wherein only the exposure system of a currently available slit-scan exposure apparatus is improved in order to obtain a resolution capable of supporting DRAMs of 256M and beyond, a problem which arises is that the effects of measurement error and a difference in level with a chip can no longer be ignored.
Specifically, as the demagnifying projection system is provided with a higher NA so as to be capable of supporting finer circuit patterns, the allowed depth of focus of the circuit pattern in the transfer step becomes progressively smaller. In order to assure an allowed depth of more than 5 μm in a state-of-the-art exposure apparatus used in rough processes, it is possible to ignore the effects of measurement error and a difference in level within a chip, which are contained in measured values obtained by continuous measurement during scanning exposure.
However, when consideration is given to dealing with DRAMs from 256M onward, the allowed depth thereof is less than 1 μm and, hence, the effects of measurement error and a difference in level within a chip, which are contained in the measured values, cannot be neglected. In other words, in a case wherein the height and inclination of a wafer surface are measured and focus is corrected so as to hold the wafer surface within the allowed depth, the fact that the wafer surface has unevenness that is dependent upon the pattern makes it essential that an offset correction conforming to the wafer surface unevenness be applied in order to make the overall chip or shot agree with the image plane at all times when scanning exposure is carried out.
In this case, an accurate offset correction amount must be carried out unless the focus measurement point (the point at which height and inclination are measured for the purpose of focus correction) of each of the shots agree at the time of offset measurement. Though this is assured with a stepper in which motion is halted and measurement performed shot by shot, it is not assured with a scanning exposure apparatus (scanner). In particular, in a case wherein a storage-type sensor is used, the offset correction is inaccurate because of a deviation between the focus measurement point and the offset measurement point. In order to deal with this problem, Japanese Patent Application Laid-Open No. 10-47915, for example, discloses resetting the storage-start timing when the position of the wafer and that of the surface position detector becomes a predetermined relative amount.
However, even the invention disclosed in Japanese Patent Application Laid-Open No. 10-47915 cannot solve the aforesaid problem completely. This is because the wafer-position control system is a digital control system, so that the position of the wafer stage and the control cycle of the wafer control system are not maintained in a predetermined relationship. That is, even when it is attempted to measure height (surface position) at the same location in the wafer plane using the same wafer-stage driving profile, the measured location actually differs each time. More specifically, the measurement position may deviate by the amount of sampling jitter, i.e., byTs×Vswhere Ts represents the control cycle of the wafer stage control system and Vs represents the traveling velocity of the wafer stage. This deviation causes a deviation of position between the position of pattern offset measurement and the position of surface measurement prevailing at the time of exposure. As a result, a defocused pattern is transferred to the wafer. It will be understood from the above expression that jitter increases when the velocity of the wafer stage increases. In particular, because the velocity of the wafer stage has been increased to achieve higher throughput lately, the influence of jitter upon focusing precision has not been negligible.
Thus, as circuit patterns shrink, the focus measurement point and offset measurement point must be made to agree with a high degree of precision.